Blink Project Status (12/22/2018 - 18:01:21)
Project File: Test.xise Parser Errors: No Errors
Module Name: Blink Implementation State: Programming File Generated
Target Device: xc6slx150-3fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
10 Warnings (10 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 25 184,304 1%  
    Number used as Flip Flops 25      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 58 92,152 1%  
    Number used as logic 57 92,152 1%  
        Number using O6 output only 34      
        Number using O5 output only 22      
        Number using O5 and O6 1      
        Number used as ROM 0      
    Number used as Memory 0 21,680 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 16 23,038 1%  
Number of MUXCYs used 24 46,076 1%  
Number of LUT Flip Flop pairs used 58      
    Number with an unused Flip Flop 33 58 56%  
    Number with an unused LUT 0 58 0%  
    Number of fully used LUT-FF pairs 25 58 43%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
7 184,304 1%  
Number of bonded IOBs 4 338 1%  
    Number of LOCed IOBs 4 4 100%  
Number of RAMB16BWERs 0 268 0%  
Number of RAMB8BWERs 0 536 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 12 0%  
Number of ILOGIC2/ISERDES2s 0 586 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 0 586 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 6 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.23      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentsá. 22. dic. 17:59:25 201809 Warnings (9 new)0
Translation ReportCurrentsá. 22. dic. 17:59:33 201801 Warning (1 new)0
Map ReportCurrentsá. 22. dic. 18:00:00 2018006 Infos (0 new)
Place and Route ReportCurrentsá. 22. dic. 18:00:25 2018003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentsá. 22. dic. 18:00:39 2018004 Infos (0 new)
Bitgen ReportCurrentsá. 22. dic. 18:01:14 2018000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentsá. 22. dic. 18:01:15 2018
WebTalk Log FileCurrentsá. 22. dic. 18:01:21 2018

Date Generated: 12/22/2018 - 18:01:22