Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s1600e
Project ID (random number) 0cd716c06eee4744a4e89be9f4d6ce7d.006FE850CD8540E494757B515C3B69C0.5 Target Package: fg320
Registration ID __0_0_0 Target Speed: -5
Date Generated 2018-12-19T23:30:07 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-3550 CPU @ 3.30GHz CPU Speed 3293 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 25-bit up counter=1
Registers=1
  • Flip-Flops=1
MiscellaneousStatistics
  • AGG_BONDED_IO=4
  • AGG_IO=4
  • AGG_SLICE=18
  • NUM_4_INPUT_LUT=32
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=31
  • NUM_LUT_RT=25
  • NUM_SLICEL=18
  • NUM_SLICE_FF=26
  • NUM_XOR=25
NetStatistics
  • NumNets_Active=48
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=14
  • NumNodesOfType_Active_CNTRLPIN=14
  • NumNodesOfType_Active_DOUBLE=27
  • NumNodesOfType_Active_DUMMY=51
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=7
  • NumNodesOfType_Active_INPUT=70
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=46
  • NumNodesOfType_Active_OUTPUT=43
  • NumNodesOfType_Active_PREBXBY=4
  • NumNodesOfType_Active_VFULLHEX=5
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=1
  • NumNodesOfType_Vcc_PREBXBY=1
  • NumNodesOfType_Vcc_VCCOUT=2
SiteStatistics
  • IBUF-DIFFS=1
  • IOB-DIFFM=2
  • IOB-DIFFS=1
  • SLICEL-SLICEM=13
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=3
  • IOB_OUTBUF=3
  • IOB_PAD=3
  • SLICEL=18
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=16
  • SLICEL_CYMUXG=15
  • SLICEL_F=17
  • SLICEL_FFX=13
  • SLICEL_FFY=13
  • SLICEL_G=15
  • SLICEL_GNDF=15
  • SLICEL_GNDG=15
  • SLICEL_XORF=13
  • SLICEL_XORG=12
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS33:1]
IOB
  • O1=[O1_INV:2] [O1:1]
IOB_OUTBUF
  • IN=[IN_INV:2] [IN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:3]
  • IOATTRBOX=[LVCMOS33:3]
  • SLEW=[SLOW:3]
SLICEL
  • BX=[BX_INV:0] [BX:2]
  • BY=[BY:0] [BY_INV:1]
  • CE=[CE:1] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:15]
  • CLK=[CLK:14] [CLK_INV:0]
  • SR=[SR:13] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:16] [0_INV:0]
  • 1=[1_INV:0] [1:16]
SLICEL_CYMUXG
  • 0=[0:15] [0_INV:0]
SLICEL_FFX
  • CK=[CK:13] [CK_INV:0]
  • D=[D:13] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:13]
  • FFX_SR_ATTR=[SRLOW:13]
  • LATCH_OR_FF=[FF:13]
  • SR=[SR:13] [SR_INV:0]
  • SYNC_ATTR=[SYNC:13]
SLICEL_FFY
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:13] [CK_INV:0]
  • D=[D:12] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:13]
  • FFY_SR_ATTR=[SRLOW:13]
  • LATCH_OR_FF=[FF:13]
  • SR=[SR:12] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:1] [SYNC:12]
SLICEL_XORF
  • 1=[1_INV:0] [1:13]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=1
  • PAD=1
IBUF_INBUF
  • IN=1
  • OUT=1
IBUF_PAD
  • PAD=1
IOB
  • O1=3
  • PAD=3
IOB_OUTBUF
  • IN=3
  • OUT=3
IOB_PAD
  • PAD=3
SLICEL
  • BX=2
  • BY=1
  • CE=1
  • CIN=15
  • CLK=14
  • COUT=15
  • F1=17
  • F2=3
  • F3=3
  • F4=3
  • G1=15
  • G2=3
  • G3=3
  • G4=3
  • SR=13
  • XB=1
  • XQ=13
  • YQ=13
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
SLICEL_CYMUXG
  • 0=15
  • 1=15
  • OUT=15
  • S0=15
SLICEL_F
  • A1=17
  • A2=3
  • A3=3
  • A4=3
  • D=17
SLICEL_FFX
  • CK=13
  • D=13
  • Q=13
  • SR=13
SLICEL_FFY
  • CE=1
  • CK=13
  • D=13
  • Q=13
  • SR=12
SLICEL_G
  • A1=15
  • A2=3
  • A3=3
  • A4=3
  • D=15
SLICEL_GNDF
  • 0=15
SLICEL_GNDG
  • 0=15
SLICEL_XORF
  • 0=13
  • 1=13
  • O=13
SLICEL_XORG
  • 0=12
  • 1=12
  • O=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1600e-fg320-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1600e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1600e-fg320-5 <ise_file> <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1600e-fg320-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1600e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1600e-fg320-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1600e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1600e-fg320-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1600e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1600e-fg320-5 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s1600e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 6 2 0 0 0 0 0
bitgen 6 6 0 0 0 0 0
map 6 6 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 8 8 0 0 0 0 0
par 6 6 0 0 0 0 0
trce 6 6 0 0 0 0 0
xst 12 12 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ise_c_project_browser.htm ( 1 ) /doc/usenglish/isehelp/pn_db_npw_create_new_project.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2018-12-19T22:41:02 PROP_intWbtProjectID=006FE850CD8540E494757B515C3B69C0
PROP_intWbtProjectIteration=5 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s1600e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_FDR=25 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_LUT4=6 NGDBUILD_NUM_MUXCY=31
NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_FDR=25 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_LUT4=6
NGDBUILD_NUM_MUXCY=31 NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1600e-5-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5