Posicion de los pines (UCF)

[jotego]

¿Podéis compartir un fichero de configuración de los pines UCF para el Xilinx ISE? ¿Y un esquemático en PDF para ver cómo está conectada cada cosa?

[antoniovillena]

Aquí va el .ucf

Código: Seleccionar todo

# Clocks & debug
NET "clk50mhz"        LOC="A10" | IOSTANDARD = LVCMOS33;
NET "testled"         LOC="T9"  | IOSTANDARD = LVCMOS33;

# Video output
NET "r<5>"            LOC="G11"   | IOSTANDARD = LVCMOS33;
NET "r<4>"            LOC="F13"   | IOSTANDARD = LVCMOS33;
NET "r<3>"            LOC="F14"   | IOSTANDARD = LVCMOS33;
NET "r<2>"            LOC="G14"   | IOSTANDARD = LVCMOS33;
NET "r<1>"            LOC="G16"   | IOSTANDARD = LVCMOS33;
NET "r<0>"            LOC="H15"   | IOSTANDARD = LVCMOS33;

NET "g<5>"            LOC="B16"   | IOSTANDARD = LVCMOS33;
NET "g<4>"            LOC="C16"   | IOSTANDARD = LVCMOS33;
NET "g<3>"            LOC="D16"   | IOSTANDARD = LVCMOS33;
NET "g<2>"            LOC="E16"   | IOSTANDARD = LVCMOS33;
NET "g<1>"            LOC="F16"   | IOSTANDARD = LVCMOS33;
NET "g<0>"            LOC="F12"   | IOSTANDARD = LVCMOS33;

NET "b<5>"            LOC="E12"   | IOSTANDARD = LVCMOS33;
NET "b<4>"            LOC="B15"   | IOSTANDARD = LVCMOS33;
NET "b<3>"            LOC="C15"   | IOSTANDARD = LVCMOS33;
NET "b<2>"            LOC="D14"   | IOSTANDARD = LVCMOS33;
NET "b<1>"            LOC="E15"   | IOSTANDARD = LVCMOS33;
NET "b<0>"            LOC="F15"   | IOSTANDARD = LVCMOS33;

NET "hsync"           LOC="G12"  | IOSTANDARD = LVCMOS33;
NET "vsync"           LOC="H16"  | IOSTANDARD = LVCMOS33;
NET "stdn"            LOC="E13"  | IOSTANDARD = LVCMOS33;

# Sound input/output
NET "audio_out_left"  LOC="H11"  | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="H13"  | IOSTANDARD = LVCMOS33;
NET "ear"             LOC="A14"  | IOSTANDARD = LVCMOS33;

# Keyboard and mouse
NET "clkps2"          LOC="M11"  | IOSTANDARD = LVCMOS33 | PULLUP;
NET "dataps2"         LOC="P12"  | IOSTANDARD = LVCMOS33 | PULLUP;
NET "mouseclk"        LOC="M10"  | IOSTANDARD = LVCMOS33 | PULLUP;
NET "mousedata"       LOC="P11"  | IOSTANDARD = LVCMOS33 | PULLUP;

# SRAM
NET "sram_addr<0>"    LOC="H14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<1>"    LOC="J16"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<2>"    LOC="J11"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<3>"    LOC="J13"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<4>"    LOC="K16"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<5>"    LOC="K11"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<6>"    LOC="L12"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<7>"    LOC="M13"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<8>"    LOC="M15"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<9>"    LOC="N14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<10>"   LOC="L14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<11>"   LOC="M14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<12>"   LOC="K14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<13>"   LOC="L13"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<14>"   LOC="J12"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<15>"   LOC="T14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<16>"   LOC="T15"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<17>"   LOC="R14"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<18>"   LOC="R16"  | IOSTANDARD = LVCMOS33;
NET "sram_data<0>"    LOC="K15"  | IOSTANDARD = LVCMOS33;
NET "sram_data<1>"    LOC="N16"  | IOSTANDARD = LVCMOS33;
NET "sram_data<2>"    LOC="L16"  | IOSTANDARD = LVCMOS33;
NET "sram_data<3>"    LOC="K12"  | IOSTANDARD = LVCMOS33;
NET "sram_data<4>"    LOC="J14"  | IOSTANDARD = LVCMOS33;
NET "sram_data<5>"    LOC="P15"  | IOSTANDARD = LVCMOS33;
NET "sram_data<6>"    LOC="P16"  | IOSTANDARD = LVCMOS33;
NET "sram_data<7>"    LOC="R15"  | IOSTANDARD = LVCMOS33;
NET "sram_we_n"       LOC="M16"  | IOSTANDARD = LVCMOS33;

# SPI Flash
NET "flash_cs_n"      LOC="T3"  | IOSTANDARD = LVCMOS33;
NET "flash_clk"       LOC="R11" | IOSTANDARD = LVCMOS33;
NET "flash_mosi"      LOC="T10" | IOSTANDARD = LVCMOS33;
NET "flash_miso"      LOC="P10" | IOSTANDARD = LVCMOS33 | PULLUP;

# SD/MMC
NET "sd_cs_n"         LOC="N9"   | IOSTANDARD = LVCMOS33;
NET "sd_clk"          LOC="T6"   | IOSTANDARD = LVCMOS33;
NET "sd_mosi"         LOC="M9"   | IOSTANDARD = LVCMOS33;
NET "sd_miso"         LOC="T7"   | IOSTANDARD = LVCMOS33;

# JOYSTICK
NET "JOY_CLK"         LOC="R12"  | IOSTANDARD = LVCMOS33; 
NET "JOY_LOAD"        LOC="T12"  | IOSTANDARD = LVCMOS33;
NET "JOY_DATA"        LOC="T13"  | IOSTANDARD = LVCMOS33;

;NET LED<1>            LOC="R9"  | IOSTANDARD = LVCMOS33;
;NET BTN<0>            LOC="T8"  | IOSTANDARD = LVCMOS33;
;NET BTN<1>            LOC="R7"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<0>     LOC="L4"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<1>     LOC="M3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<2>     LOC="M4"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<3>     LOC="N3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<4>     LOC="R2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<5>     LOC="R1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<6>     LOC="P2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<7>     LOC="P1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<8>     LOC="N1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<9>     LOC="M1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<10>    LOC="L3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<11>    LOC="L1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_ADDR<12>    LOC="K1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<0>     LOC="A3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<1>     LOC="A2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<2>     LOC="B3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<3>     LOC="B2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<4>     LOC="C3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<5>     LOC="C2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<6>     LOC="D3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<7>     LOC="E3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<8>     LOC="G1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<9>     LOC="F1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<10>    LOC="F2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<11>    LOC="E1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<12>    LOC="E2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<13>    LOC="D1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<14>    LOC="C1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DATA<15>    LOC="B1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DQML        LOC="F3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_DQMH        LOC="H2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_BA<0>       LOC="K3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_BA<1>       LOC="K2"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_nWE         LOC="G3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_nCAS        LOC="H3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_nRAS        LOC="J4"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_nCS         LOC="J3"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_CLK         LOC="H1"  | IOSTANDARD = LVCMOS33;
;NET SDRAM_CKE         LOC="J1"  | IOSTANDARD = LVCMOS33;

[antoniovillena]

Los esquemáticos los tienes aquí. Los de la placa FPGA en este link:

https://github.com/ChinaQMTECH/QM_XC6SLX16_SDRAM

[jotego]

¡Muchas gracias!