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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:08:24 12/22/2018
// Design Name:
// Module Name: Blink
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Blink(
input clk,
output led_green,
output led_blue,
output led_red
);
parameter CLK_FREQ = 20000000;
parameter BLINK_FREQ = 1;
parameter CNT_MAX = CLK_FREQ/BLINK_FREQ/2-1;
reg[32:0] cnt;
reg blink;
always@(posedge clk)
begin
if (cnt==CNT_MAX) begin
cnt <= 0;
blink <= !blink;
end else begin
cnt <= cnt + 1;
end;
end;
assign led_red = !blink;
assign led_green = !blink;
assign led_blue = blink;
endmodule
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# Pano Logic Zero Client G2 Constraints File
# VCCAUX is 2.5 Volts
CONFIG VCCAUX = "2.5";
# 25 MHz System Clock
NET "clk" LOC = Y13 | IOSTANDARD = LVCMOS33;
TIMESPEC TS_CLK = PERIOD "clk" 25 MHz HIGH 50%;
NET "clk" TNM_NET = clk_osc;
# Pano Button LED Output, Active High
NET "led_red" LOC = E12 | IOSTANDARD = LVCMOS33;
NET "led_blue" LOC = H13 | IOSTANDARD = LVCMOS33;
NET "led_green" LOC = F13 | IOSTANDARD = LVCMOS33;