https://github.com/tomverbeure/panologic
Pinout of the JTAG is as follows:
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1. VCC
2. TDI
3. TMS
4. TDO
5. TCK
6. GND (it is placed to the right side of the picture)
2) Connect the cables to the USB-Blaster follow this picture from
http://www.zxuno.com/forum/viewtopic.php?t=432
3) Download the last UrJTAG version for Windows from here:
https://phoenixnap.dl.sourceforge.net/p ... 31.tar.gz
4) Decompress the file in one folder called for example UrJTAG
5) Convert the BIT file to SVF file with impact in Xillinx ISE.
Read the 2nd page of the next doc:
https://www.xilinx.com/support/documen ... pp503.pdf
6) Copy the SVF in the path of UrJTAG
7) In a terminal type:
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jtag
8) type:
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cable usbblaster
detect
9) Now, we are going to program the FPGA.
Note: In my case my file is led.svf
Type:
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svf led.svf progress
This procedure worked with the Logic Pano G1. It is supposed that it works with the G2 version too, but I cannot confirm it.