Moderador: antoniovillena
El precio sería de 10 euros el kit y 15 euros montado en caso de que se lleve a cabo la tirada.
Hecho.
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#========================================================
# clock
#========================================================
NET "clk" LOC="A10" | IOSTANDARD=LVCMOS33;
#========================================================
# buttons & switches
#========================================================
# 6 push buttons
NET "bot<0>" LOC="A14" | IOSTANDARD=LVCMOS33 | PULLUP; #up right
NET "bot<1>" LOC="A9" | IOSTANDARD=LVCMOS33 | PULLUP; #down right
NET "bot<2>" LOC="A11" | IOSTANDARD=LVCMOS33 | PULLUP; #1 left
NET "bot<3>" LOC="B14" | IOSTANDARD=LVCMOS33 | PULLUP; #2 left
NET "bot<4>" LOC="A13" | IOSTANDARD=LVCMOS33 | PULLUP; #3 left
NET "bot<5>" LOC="A12" | IOSTANDARD=LVCMOS33 | PULLUP; #4 left
# 8 slide switches
NET "sw<0>" LOC="E11" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<1>" LOC="F10" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<2>" LOC="C10" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<3>" LOC="A4" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<4>" LOC="A5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<5>" LOC="A6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<6>" LOC="A7" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "sw<7>" LOC="A8" | IOSTANDARD=LVCMOS33 | PULLUP;
#========================================================
# 4-digit time-multiplexed 7-segment LED display
#========================================================
# digit enable
NET "an<0>" LOC="N5" | IOSTANDARD=LVCMOS33;
NET "an<1>" LOC="D8" | IOSTANDARD=LVCMOS33;
NET "an<2>" LOC="F9" | IOSTANDARD=LVCMOS33;
NET "an<3>" LOC="D6" | IOSTANDARD=LVCMOS33;
# 7-segment led segments
NET "sseg<7>" LOC="E7" | IOSTANDARD=LVCMOS33; # decimal point
NET "sseg<6>" LOC="C8" | IOSTANDARD=LVCMOS33; # segment a
NET "sseg<5>" LOC="E6" | IOSTANDARD=LVCMOS33; # segment b
NET "sseg<4>" LOC="C6" | IOSTANDARD=LVCMOS33; # segment c
NET "sseg<3>" LOC="M6" | IOSTANDARD=LVCMOS33; # segment d
NET "sseg<2>" LOC="F7" | IOSTANDARD=LVCMOS33; # segment e
NET "sseg<1>" LOC="D9" | IOSTANDARD=LVCMOS33; # segment f
NET "sseg<0>" LOC="P4" | IOSTANDARD=LVCMOS33; # segment g
#========================================================
# 8 discrete led
#========================================================
NET "led<0>" LOC="B6" | IOSTANDARD=LVCMOS33;
NET "led<1>" LOC="C7" | IOSTANDARD=LVCMOS33;
NET "led<2>" LOC="B8" | IOSTANDARD=LVCMOS33;
NET "led<3>" LOC="C9" | IOSTANDARD=LVCMOS33;
NET "led<4>" LOC="B10" | IOSTANDARD=LVCMOS33;
NET "led<5>" LOC="C11" | IOSTANDARD=LVCMOS33;
NET "led<6>" LOC="B12" | IOSTANDARD=LVCMOS33;
NET "led<7>" LOC="C13" | IOSTANDARD=LVCMOS33;
Código: Seleccionar todo
-- Listing 4.13
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disp_mux is
port(
clk, reset: in std_logic;
in3, in2, in1, in0: in std_logic_vector(6 downto 0);
point: in std_logic;
colon: in std_logic;
an: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end disp_mux ;
architecture arch of disp_mux is
-- refreshing rate around 800 Hz (50MHz/2^16)
constant N: integer:=18;
signal q_reg, q_next: unsigned(N-1 downto 0);
signal sel: std_logic_vector(1 downto 0);
begin
-- register
process(clk,reset)
begin
if reset='1' then
q_reg <= (others=>'0');
elsif (clk'event and clk='1') then
q_reg <= q_next;
end if;
end process;
-- next-state logic for the counter
q_next <= q_reg + 1;
-- 2 MSBs of counter to control 4-to-1 multiplexing
-- and to generate active-low enable signal
sel <= std_logic_vector(q_reg(N-1 downto N-2));
process(sel,in0,in1,in2,in3,colon,point)
begin
case sel is
when "00" =>
an <= "1110";
sseg <= '1' & in0;
when "01" =>
an <= "1101";
sseg <= '1' & in1;
when "10" =>
an <= "1011";
sseg <= colon & in2;
when others =>
an <= "0111";
sseg <= point & in3;
end case;
end process;
end arch;
Código: Seleccionar todo
-- Listing 3.12
library ieee;
use ieee.std_logic_1164.all;
entity hex_to_sseg is
port(
hex: in std_logic_vector(3 downto 0);
sseg: out std_logic_vector(6 downto 0)
);
end hex_to_sseg;
architecture arch of hex_to_sseg is
begin
with hex select
sseg <=
"0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010", --a
"1100000" when "1011", --b
"0110001" when "1100", --c
"1000010" when "1101", --d
"0110000" when "1110", --e
"0111000" when others; --f
end arch;
Código: Seleccionar todo
-- Listing 3.13
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hex_to_sseg_test is
port(
clk: in std_logic;
bot: in std_logic_vector(5 downto 0);
sw: in std_logic_vector(7 downto 0);
led: out std_logic_vector(7 downto 0);
an: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end hex_to_sseg_test;
architecture arch of hex_to_sseg_test is
signal inc: std_logic_vector(7 downto 0);
signal led3, led2, led1, led0: std_logic_vector(6 downto 0);
begin
led <= (sw(7 downto 6) & not bot);
-- increment input
inc <= std_logic_vector(unsigned(sw) + 1);
-- instantiate four instances of hex decoders
-- instance for 4 LSBs of input
sseg_unit_0: entity work.hex_to_sseg
port map(hex=>sw(3 downto 0), sseg=>led0);
-- instance for 4 MSBs of input
sseg_unit_1: entity work.hex_to_sseg
port map(hex=>sw(7 downto 4), sseg=>led1);
-- instance for 4 LSBs of incremented value
sseg_unit_2: entity work.hex_to_sseg
port map(hex=>inc(3 downto 0), sseg=>led2);
-- instance for 4 MSBs of incremented value
sseg_unit_3: entity work.hex_to_sseg
port map(hex=>inc(7 downto 4), sseg=>led3);
-- instantiate 7-seg LED display time-multiplexing module
disp_unit: entity work.disp_mux
port map(
clk=>clk, reset=>'0',
in0=>led0, in1=>led1, in2=>led2, in3=>led3,
point=>'1', colon=>'0',
an=>an, sseg=>sseg);
end arch;